more rsa improvement
authorNIIBE Yutaka <gniibe@fsij.org>
Fri, 27 May 2011 02:11:41 +0000 (11:11 +0900)
committerNIIBE Yutaka <gniibe@fsij.org>
Fri, 27 May 2011 02:11:41 +0000 (11:11 +0900)
ChangeLog
polarssl-0.14.0/include/polarssl/bn_mul.h

index dcb5565..0d783c1 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,8 @@
+2011-05-27  NIIBE Yutaka  <gniibe@fsij.org>
+
+       * polarssl-0.14.0/include/polarssl/bn_mul.h [__arm__]
+       (MULADDC_HUIT): New.
+
 2011-05-26  NIIBE Yutaka  <gniibe@fsij.org>
 
        * polarssl-0.14.0/include/polarssl/bn_mul.h [__arm__]
index afcbdc2..f17a48a 100644 (file)
 
 #if defined(__arm__)
 
+#define MULADDC_HUIT                        \
+    asm( "ldmia  r0!, { r4, r5 } " );       \
+    asm( "ldmia  r1, { r8, r9 }  " );       \
+    asm( "umull  r6, r7, r3, r4  " );       \
+    asm( "adcs   r6, r6, r2      " );       \
+    asm( "adc    r7, r7, #0      " );       \
+    asm( "adds   r8, r8, r6      " );       \
+    asm( "umull  r6, r2, r3, r5  " );       \
+    asm( "adcs   r6, r6, r7      " );       \
+    asm( "adc    r2, r2, #0      " );       \
+    asm( "adds   r9, r9, r6      " );       \
+    asm( "stmia  r1!, { r8, r9 } " );       \
+    asm( "ldmia  r0!, { r4, r5 } " );       \
+    asm( "ldmia  r1, { r8, r9 }  " );       \
+    asm( "umull  r6, r7, r3, r4  " );       \
+    asm( "adcs   r6, r6, r2      " );       \
+    asm( "adc    r7, r7, #0      " );       \
+    asm( "adds   r8, r8, r6      " );       \
+    asm( "umull  r6, r2, r3, r5  " );       \
+    asm( "adcs   r6, r6, r7      " );       \
+    asm( "adc    r2, r2, #0      " );       \
+    asm( "adds   r9, r9, r6      " );       \
+    asm( "stmia  r1!, { r8, r9 } " );       \
+    asm( "ldmia  r0!, { r4, r5 } " );       \
+    asm( "ldmia  r1, { r8, r9 }  " );       \
+    asm( "umull  r6, r7, r3, r4  " );       \
+    asm( "adcs   r6, r6, r2      " );       \
+    asm( "adc    r7, r7, #0      " );       \
+    asm( "adds   r8, r8, r6      " );       \
+    asm( "umull  r6, r2, r3, r5  " );       \
+    asm( "adcs   r6, r6, r7      " );       \
+    asm( "adc    r2, r2, #0      " );       \
+    asm( "adds   r9, r9, r6      " );       \
+    asm( "stmia  r1!, { r8, r9 } " );       \
+    asm( "ldmia  r0!, { r4, r5 } " );       \
+    asm( "ldmia  r1, { r8, r9 }  " );       \
+    asm( "umull  r6, r7, r3, r4  " );       \
+    asm( "adcs   r6, r6, r2      " );       \
+    asm( "adc    r7, r7, #0      " );       \
+    asm( "adds   r8, r8, r6      " );       \
+    asm( "umull  r6, r2, r3, r5  " );       \
+    asm( "adcs   r6, r6, r7      " );       \
+    asm( "adc    r2, r2, #0      " );       \
+    asm( "adds   r9, r9, r6      " );       \
+    asm( "stmia  r1!, { r8, r9 } " );
+
 #define MULADDC_INIT                            \
     asm( "ldr    r0, %0         " :: "m" (s));  \
     asm( "ldr    r1, %0         " :: "m" (d));  \
     asm( "str    r2, %0         " : "=m" (c));  \
     asm( "str    r1, %0         " : "=m" (d));  \
     asm( "str    r0, %0         " : "=m" (s) :: \
-    "r0", "r1", "r2", "r3", "r4", "r5" );
+    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9");
 
 #endif /* ARMv3 */