STBEE support
authorNIIBE Yutaka <gniibe@fsij.org>
Wed, 26 Jan 2011 02:30:01 +0000 (11:30 +0900)
committerNIIBE Yutaka <gniibe@fsij.org>
Wed, 26 Jan 2011 02:30:01 +0000 (11:30 +0900)
AUTHORS
ChangeLog
NEWS
boards/STBEE/board.c [new file with mode: 0644]
boards/STBEE/board.h [new file with mode: 0644]
boards/STBEE/board.mk [new file with mode: 0644]
boards/STBEE/mcuconf.h [new file with mode: 0644]
src/configure
tool/dfuse.py

diff --git a/AUTHORS b/AUTHORS
index 04c16ef..b9270bb 100644 (file)
--- a/AUTHORS
+++ b/AUTHORS
@@ -7,6 +7,11 @@ Kaz Kojima:
 
 NIIBE Yutaka:
     Founder of the project.
+    Added STBee support:
+       boards/STBEE/board.c
+       boards/STBEE/board.h
+       boards/STBEE/board.mk
+       boards/STBEE/mcuconf.h
     Added STM8S Discovery Kit support:
        boards/STM8S_DISCOVERY/board.c
        boards/STM8S_DISCOVERY/board.h
@@ -45,5 +50,6 @@ NIIBE Yutaka:
        src/call-rsa.c
        src/random.c
        src/pin-cir.c
+       src/pin-dial.c
        *
        and others.
index f9769cc..0fa8c8e 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,14 @@
+2011-01-26  NIIBE Yutaka  <gniibe@fsij.org>
+
+       * boards/STBEE/mcuconf.h: New.
+       * boards/STBEE/board.mk: New.
+       * boards/STBEE/board.h: New.
+       * boards/STBEE/board.c: New.
+
+       * tool/dfuse.py (DFU_STM32.verify): Add double ll_clear_status.
+
+       * src/configure (target): Add STBEE.
+
 2011-01-25  NIIBE Yutaka  <gniibe@fsij.org>
 
        * src/openpgp.c (cmd_pso): Support DigestInfo by MD5 (for opensc).
diff --git a/NEWS b/NEWS
index 929d4c4..1e1c829 100644 (file)
--- a/NEWS
+++ b/NEWS
@@ -1,5 +1,22 @@
 Gnuk NEWS - User visible changes
 
+* Major changes in Gnuk 0.9
+
+  Released 2011-01-XX, by NIIBE Yutaka
+
+** Better interoperability to OpenSC.
+Gnuk is not yet supported by OpenSC, but it should be.  With this
+changes in Gnuk, it could be relatively easily possible to support
+Gnuk Token by OpenSC with a few changes to libopensc/card-openpgp.c,
+libopensc/pkcs15-openpgp.c and pkcs11/framework-pkcs15.c.
+
+** New board support "STBEE"
+STBEE is a board by Strawberry Linux Co., Ltd., and it has
+STM32F103VET6 on the board.  The chip is High Density CPU with 512KB
+flash memory and many I/O.  If you want to connect sensor, display,
+etc., this board would be good candidate.
+
+
 * Major changes in Gnuk 0.8
 
   Released 2011-01-19, by NIIBE Yutaka
diff --git a/boards/STBEE/board.c b/boards/STBEE/board.c
new file mode 100644 (file)
index 0000000..882d79e
--- /dev/null
@@ -0,0 +1,159 @@
+#include "config.h"
+#include "ch.h"
+#include "hal.h"
+
+#include "../common/hwinit.c"
+
+void
+hwinit0 (void)
+{
+  hwinit0_common ();
+}
+
+void
+hwinit1 (void)
+{
+  hwinit1_common ();
+
+#if defined(PINPAD_SUPPORT)
+#if defined(PINPAD_CIR_SUPPORT)
+  /* EXTI0 <= PB0 */
+  AFIO->EXTICR[0] = AFIO_EXTICR1_EXTI0_PB;
+  EXTI->IMR = 0;
+  EXTI->FTSR = EXTI_FTSR_TR0;
+  NVICEnableVector(EXTI0_IRQn,
+                  CORTEX_PRIORITY_MASK(CORTEX_MINIMUM_PRIORITY));
+
+  /* TIM3 */
+  RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
+  RCC->APB1RSTR = RCC_APB1RSTR_TIM3RST;
+  RCC->APB1RSTR = 0;
+  NVICEnableVector(TIM3_IRQn,
+                  CORTEX_PRIORITY_MASK(CORTEX_MINIMUM_PRIORITY));
+  TIM3->CR1 = TIM_CR1_URS | TIM_CR1_ARPE; /* Don't enable TIM3 for now */
+  TIM3->CR2 = TIM_CR2_TI1S;
+  TIM3->SMCR = TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_SMS_2;
+  TIM3->DIER = 0;              /* Disable interrupt for now */
+  TIM3->CCMR1 = TIM_CCMR1_CC1S_0 | TIM_CCMR1_IC1F_0 | TIM_CCMR1_IC1F_3
+    | TIM_CCMR1_CC2S_1 | TIM_CCMR1_IC2F_0 | TIM_CCMR1_IC2F_3;
+  TIM3->CCMR2 = 0;
+  TIM3->CCER =  TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC2P;
+  TIM3->PSC = 72 - 1;          /* 1 MHz */
+  TIM3->ARR = 18000;           /* 18 ms */
+  /* Generate UEV to upload PSC and ARR */
+  TIM3->EGR = TIM_EGR_UG;      
+#elif defined(PINPAD_DIAL_SUPPORT)
+  /* EXTI2 <= PB2 */
+  AFIO->EXTICR[0] = AFIO_EXTICR1_EXTI2_PB;
+  EXTI->IMR = 0;
+  EXTI->FTSR = EXTI_FTSR_TR2;
+  NVICEnableVector(EXTI2_IRQn,
+                  CORTEX_PRIORITY_MASK(CORTEX_MINIMUM_PRIORITY));
+
+  /* TIM4 */
+  RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;
+  RCC->APB1RSTR = RCC_APB1RSTR_TIM4RST;
+  RCC->APB1RSTR = 0;
+
+  TIM4->CR1 = TIM_CR1_URS |  TIM_CR1_ARPE | TIM_CR1_CKD_1;
+  TIM4->CR2 = 0;
+  TIM4->SMCR = TIM_SMCR_SMS_0;
+  TIM4->DIER = 0;              /* no interrupt */
+  TIM4->CCMR1 = TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0
+    | TIM_CCMR1_IC1F_0 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_3
+    | TIM_CCMR1_IC2F_0 | TIM_CCMR1_IC2F_1 | TIM_CCMR1_IC2F_2 | TIM_CCMR1_IC2F_3;
+  TIM4->CCMR2 = 0;
+  TIM4->CCER = 0;
+  TIM4->PSC = 0;
+  TIM4->ARR = 31;
+  /* Generate UEV to upload PSC and ARR         */
+  TIM4->EGR = TIM_EGR_UG;
+#endif
+#endif
+}
+
+void
+USB_Cable_Config (FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+    palClearPad (IOPORT4, GPIOD_USB_ENABLE);
+  else
+    palSetPad (IOPORT4, GPIOD_USB_ENABLE);
+}
+
+void
+set_led (int value)
+{
+  if (value)
+    palClearPad (IOPORT4, GPIOD_LED1);
+  else
+    palSetPad (IOPORT4, GPIOD_LED1);
+}
+
+#if defined(PINPAD_SUPPORT)
+#if defined(PINPAD_CIR_SUPPORT)
+void
+cir_ext_disable (void)
+{
+  EXTI->PR = EXTI_PR_PR0;
+  EXTI->IMR &= ~EXTI_IMR_MR0;
+}
+
+void
+cir_ext_enable (void)
+{
+  EXTI->IMR |= EXTI_IMR_MR0;
+}
+
+extern void cir_ext_interrupt (void);
+extern void cir_timer_interrupt (void);
+
+CH_IRQ_HANDLER (EXTI0_IRQHandler)
+{
+  CH_IRQ_PROLOGUE ();
+  chSysLockFromIsr ();
+
+  cir_ext_interrupt ();
+
+  chSysUnlockFromIsr ();
+  CH_IRQ_EPILOGUE ();
+}
+
+CH_IRQ_HANDLER (TIM3_IRQHandler)
+{
+  CH_IRQ_PROLOGUE();
+  chSysLockFromIsr();
+
+  cir_timer_interrupt ();
+
+  chSysUnlockFromIsr();
+  CH_IRQ_EPILOGUE();
+}
+#elif defined(PINPAD_DIAL_SUPPORT)
+void
+dial_sw_disable (void)
+{
+  EXTI->PR = EXTI_PR_PR2;
+  EXTI->IMR &= ~EXTI_IMR_MR2;
+}
+
+void
+dial_sw_enable (void)
+{
+  EXTI->IMR |= EXTI_IMR_MR2;
+}
+
+extern void dial_sw_interrupt (void);
+
+CH_IRQ_HANDLER (EXTI2_IRQHandler)
+{
+  CH_IRQ_PROLOGUE ();
+  chSysLockFromIsr ();
+
+  dial_sw_interrupt ();
+
+  chSysUnlockFromIsr ();
+  CH_IRQ_EPILOGUE ();
+}
+#endif
+#endif
diff --git a/boards/STBEE/board.h b/boards/STBEE/board.h
new file mode 100644 (file)
index 0000000..6e2e74d
--- /dev/null
@@ -0,0 +1,180 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+                                      ---
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes ChibiOS/RT, without being obliged to provide
+    the source code for any proprietary components. See the file exception.txt
+    for full details of how and when the exception can be applied.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "config.h"
+/*
+ * Setup for the STBee board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_STBEE
+#define BOARD_NAME "STBee"
+
+#if defined(PINPAD_SUPPORT)
+#define HAVE_7SEGLED   1
+#endif
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK            32768
+#define STM32_HSECLK            12000000
+
+/*
+ * MCU type, this macro is used by both the ST library and the ChibiOS/RT
+ * native STM32 HAL.
+ */
+#define STM32F10X_HD
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOD_LED1             4
+#define GPIOD_USB_ENABLE       3
+#define GPIOA_USER             0
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ *   0 - Analog input.
+ *   1 - Push Pull output 10MHz.
+ *   2 - Push Pull output 2MHz.
+ *   3 - Push Pull output 50MHz.
+ *   4 - Digital input.
+ *   5 - Open Drain output 10MHz.
+ *   6 - Open Drain output 2MHz.
+ *   7 - Open Drain output 50MHz.
+ *   8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ *   9 - Alternate Push Pull output 10MHz.
+ *   A - Alternate Push Pull output 2MHz.
+ *   B - Alternate Push Pull output 50MHz.
+ *   C - Reserved.
+ *   D - Alternate Open Drain output 10MHz.
+ *   E - Alternate Open Drain output 2MHz.
+ *   F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+
+#if defined(PINPAD_SUPPORT)
+/*
+ * Port A setup.
+ * PA6  - (TIM3_CH1) input with pull-up
+ * PA7  - (TIM3_CH2) input with pull-down
+ * PA11 - input with pull-up (USBDM)
+ * PA12 - input with pull-up (USBDP)
+ * Everything input with pull-up except:
+ * PA0  - Normal input.
+ */
+#define VAL_GPIOACRL            0x88888884      /*  PA7...PA0 */
+#define VAL_GPIOACRH            0x88888888      /* PA15...PA8 */
+#define VAL_GPIOAODR            0xFFFFFF7F
+
+/* Port B setup. */
+#define GPIOB_CIR              0
+#define GPIOB_BUTTON            2
+#define GPIOB_ROT_A             6
+#define GPIOB_ROT_B             7
+
+#define GPIOB_7SEG_DP           15
+#define GPIOB_7SEG_A            14
+#define GPIOB_7SEG_B            13
+#define GPIOB_7SEG_C            12
+#define GPIOB_7SEG_D            11
+#define GPIOB_7SEG_E            10
+#define GPIOB_7SEG_F            9
+#define GPIOB_7SEG_G            8
+
+#define VAL_GPIOBCRL            0x88888888      /*  PB7...PB0 */
+#define VAL_GPIOBCRH            0x66666666      /* PB15...PB8 */
+#define VAL_GPIOBODR            0xFFFFFFFF
+#else
+/*
+ * Port A setup.
+ * PA11 - input with pull-up (USBDM)
+ * PA12 - input with pull-up (USBDP)
+ * Everything input with pull-up except:
+ * PA0 - Normal input.
+ */
+#define VAL_GPIOACRL            0x88888884      /*  PA7...PA0 */
+#define VAL_GPIOACRH            0x88888888      /* PA15...PA8 */
+#define VAL_GPIOAODR            0xFFFFFFFF
+
+/* Port B setup. */
+/* Everything input with pull-up */
+#define VAL_GPIOBCRL            0x88888888      /*  PB7...PB0 */
+#define VAL_GPIOBCRH            0x88888888      /* PB15...PB8 */
+#define VAL_GPIOBODR            0xFFFFFFFF
+#endif
+
+/*
+ * Port C setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOCCRL            0x88888888      /*  PC7...PC0 */
+#define VAL_GPIOCCRH            0x88888888      /* PC15...PC8 */
+#define VAL_GPIOCODR            0xFFFFFFFF
+
+/*
+ * Port D setup.
+ * Everything input with pull-up except:
+ * PD3  - Push pull output  (USB ENABLE 1:DISABLE 0:ENABLE) 2MHz
+ * PD4  - Open Drain output 2MHz (LED1).
+ */
+#define VAL_GPIODCRL            0x88862888      /*  PD7...PD0 */
+#define VAL_GPIODCRH            0x88888888      /* PD15...PD8 */
+#define VAL_GPIODODR            0xFFFFFFFF
+
+/*
+ * Port E setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOECRL            0x88888888      /*  PE7...PE0 */
+#define VAL_GPIOECRH            0x88888888      /* PE15...PE8 */
+#define VAL_GPIOEODR            0xFFFFFFFF
+
+/*
+ * Port F setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOFCRL            0x88888888      /*  PF7...PF0 */
+#define VAL_GPIOFCRH            0x88888888      /* PF15...PF8 */
+#define VAL_GPIOFODR            0xFFFFFFFF
+
+/*
+ * Port G setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOGCRL            0x88888888      /*  PG7...PG0 */
+#define VAL_GPIOGCRH            0x88888888      /* PG15...PG8 */
+#define VAL_GPIOGODR            0xFFFFFFFF
+#endif /* _BOARD_H_ */
diff --git a/boards/STBEE/board.mk b/boards/STBEE/board.mk
new file mode 100644 (file)
index 0000000..1d5c6e0
--- /dev/null
@@ -0,0 +1,6 @@
+# List of all the board related files.
+BOARDSRC = ../boards/STBEE/board.c \
+       ../boards/common/hw_config.c
+
+# Required include directories
+BOARDINC = ../boards/STBEE
diff --git a/boards/STBEE/mcuconf.h b/boards/STBEE/mcuconf.h
new file mode 100644 (file)
index 0000000..c2bc654
--- /dev/null
@@ -0,0 +1,107 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+                                      ---
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes ChibiOS/RT, without being obliged to provide
+    the source code for any proprietary components. See the file exception.txt
+    for full details of how and when the exception can be applied.
+*/
+
+/*
+ * STM32 drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the driver
+ * is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0       Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3        Lowest...Highest.
+ */
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_SW                    STM32_SW_PLL
+#define STM32_PLLSRC                STM32_PLLSRC_HSE
+#define STM32_PLLXTPRE              STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE          6
+#define STM32_HPRE                  STM32_HPRE_DIV1
+#define STM32_PPRE1                 STM32_PPRE1_DIV2
+#define STM32_PPRE2                 STM32_PPRE2_DIV2
+#define STM32_ADCPRE                STM32_ADCPRE_DIV4
+#define STM32_MCO                   STM32_MCO_NOCLOCK
+
+/*
+ * ADC driver system settings.
+ */
+#define USE_STM32_ADC1              FALSE
+#define STM32_ADC1_DMA_PRIORITY     3
+#define STM32_ADC1_IRQ_PRIORITY     5
+#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt()
+
+/*
+ * CAN driver system settings.
+ */
+#define USE_STM32_CAN1              FALSE
+#define STM32_CAN1_IRQ_PRIORITY     11
+
+/*
+ * PWM driver system settings.
+ */
+#define USE_STM32_PWM1              FALSE
+#define USE_STM32_PWM2              FALSE
+#define USE_STM32_PWM3              FALSE
+#define USE_STM32_PWM4              FALSE
+#define STM32_PWM1_IRQ_PRIORITY     7
+#define STM32_PWM2_IRQ_PRIORITY     7
+#define STM32_PWM3_IRQ_PRIORITY     7
+#define STM32_PWM4_IRQ_PRIORITY     7
+
+/*
+ * SERIAL driver system settings.
+ */
+#define USE_STM32_USART1            FALSE
+#define USE_STM32_USART2            FALSE
+#define USE_STM32_USART3            FALSE
+#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
+#define USE_STM32_UART4             FALSE
+#define USE_STM32_UART5             FALSE
+#endif
+#define STM32_USART1_PRIORITY       12
+#define STM32_USART2_PRIORITY       12
+#define STM32_USART3_PRIORITY       12
+#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
+#define STM32_UART4_PRIORITY        12
+#define STM32_UART5_PRIORITY        12
+#endif
+
+/*
+ * SPI driver system settings.
+ */
+#define USE_STM32_SPI1              FALSE
+#define USE_STM32_SPI2              FALSE
+#define STM32_SPI1_DMA_PRIORITY     2
+#define STM32_SPI2_DMA_PRIORITY     2
+#define STM32_SPI1_IRQ_PRIORITY     10
+#define STM32_SPI2_IRQ_PRIORITY     10
+#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt()
index 60e9681..b79fc59 100755 (executable)
@@ -88,6 +88,8 @@ Configuration:
                           STM32_PRIMER2
                           CQ_STARM
                           STBEE_MINI
+                          STM8S_DISCOVERY
+                          STBEE
   --enable-debug       debug with virtual COM port     [no]
   --enable-pinpad={cir,dial}
                        PIN input device support        [no]
@@ -118,7 +120,14 @@ CQ_STARM|STBEE_MINI)
   fi  ;;
 STM32_PRIMER2)
   FLASH_PAGE_SIZE=2048
+  FLASH_SIZE=512
   ;;
+STBEE)
+  FLASH_PAGE_SIZE=2048
+  FLASH_SIZE=512
+  if test "$with_dfu" = "default"; then
+    with_dfu=yes;
+  fi  ;;
 STM8S_DISCOVERY)
   FLASH_SIZE=64
   ;;
index ba1293f..3b6e52f 100755 (executable)
@@ -298,6 +298,8 @@ class DFU_STM32:
                     sys.stdout.flush()
                 addr += 1024
                 i += 1
+            self.ll_clear_status()
+            self.ll_clear_status()
         self.ll_clear_status()
         sys.stdout.write("\n")
         sys.stdout.flush()