ADC info consolidated into the driver
authorNIIBE Yutaka <gniibe@fsij.org>
Tue, 14 Jul 2015 12:18:35 +0000 (21:18 +0900)
committerNIIBE Yutaka <gniibe@fsij.org>
Tue, 14 Jul 2015 12:18:35 +0000 (21:18 +0900)
ChangeLog
src/adc_stm32f103.c
src/configure

index de6e66a..dd891f1 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,5 +1,10 @@
 2015-07-14  Niibe Yutaka  <gniibe@fsij.org>
 
+       * src/configurew (sys1_compat): Fix assignment syntax.
+
+       * src/adc_stm32f103.c (get_adc_config): New.  Consolidate knowlege
+       of boards for ADC usage.
+
        * src/neug.c: Remove inclusion of "board.h".
 
        * tool/neug_check.py (field): New field 'Board'.
index 85d9030..356d96b 100644 (file)
@@ -3,7 +3,8 @@
  *                   In this ADC driver, there are NeuG specific parts.
  *                   You need to modify to use this as generic ADC driver.
  *
- * Copyright (C) 2011, 2012, 2013 Free Software Initiative of Japan
+ * Copyright (C) 2011, 2012, 2013, 2015
+ *               Free Software Initiative of Japan
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
  * This file is a part of NeuG, a True Random Number Generator
@@ -32,6 +33,8 @@
 #include "stm32f103.h"
 #include "adc.h"
 
+#include "config.h"
+
 #define NEUG_CRC32_COUNTS 4
 
 #define STM32_ADC_ADC1_DMA_PRIORITY         2
                               | ADC_SQR3_SQ4_N(ADC_CHANNEL_VREFINT)     
 #define NEUG_ADC_SETTING1_NUM_CHANNELS 4
 
-#if !defined(NEUG_ADC_SETTING2_SMPR1)
-#define NEUG_ADC_SETTING2_SMPR1 0
-#define NEUG_ADC_SETTING2_SMPR2 ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5)    \
-                              | ADC_SMPR2_SMP_AN1(ADC_SAMPLE_1P5)
-#define NEUG_ADC_SETTING2_SQR3  ADC_SQR3_SQ1_N(ADC_CHANNEL_IN0)      \
-                              | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN1)
-#define NEUG_ADC_SETTING2_NUM_CHANNELS 2
-#endif
-
 
 /*
  * Do calibration for both of ADCs.
@@ -133,9 +127,67 @@ void adc_init (void)
   RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN | RCC_APB2ENR_ADC2EN);
 }
 
+#include "sys.h"
+#if defined(HAVE_SYS_H)
+# define SYS_BOARD_ID sys_board_id
+#else
+# include "board.h"
+# define SYS_BOARD_ID BOARD_ID
+#endif
+
+static void
+get_adc_config (uint32_t config[4])
+{
+  config[2] = ADC_SQR1_NUM_CH(2);
+  switch (SYS_BOARD_ID)
+    {
+    case BOARD_ID_FST_01:
+      config[0] = 0;
+      config[1] = ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5)
+               | ADC_SMPR2_SMP_AN9(ADC_SAMPLE_1P5);
+      config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN0)
+               | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN9);
+      break;
+
+    case BOARD_ID_OLIMEX_STM32_H103:
+    case BOARD_ID_STBEE:
+      config[0] = ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5) 
+               | ADC_SMPR1_SMP_AN11(ADC_SAMPLE_1P5);
+      config[1] = 0;
+      config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10)
+               | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN11);
+      break;
+
+    case BOARD_ID_STBEE_MINI:
+      config[0] = 0;
+      config[1] = ADC_SMPR2_SMP_AN1(ADC_SAMPLE_1P5)
+               | ADC_SMPR2_SMP_AN2(ADC_SAMPLE_1P5);
+      config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN1)
+               | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN2);
+      break;
+
+    case BOARD_ID_CQ_STARM:
+    case BOARD_ID_FST_01_00:
+    case BOARD_ID_MAPLE_MINI:
+    case BOARD_ID_STM32_PRIMER2:
+    case BOARD_ID_STM8S_DISCOVERY:
+    default:
+      config[0] = 0;
+      config[1] = ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5)
+               | ADC_SMPR2_SMP_AN1(ADC_SAMPLE_1P5);
+      config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN0)
+               | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN1);
+      break;
+    }
+}
+
 
 void adc_start (void)
 {
+  uint32_t config[4];
+
+  get_adc_config (config);
+
   /* Use DMA channel 1.  */
   RCC->AHBENR |= RCC_AHBENR_DMA1EN;
   DMA1_Channel1->CCR = STM32_DMA_CCR_RESET_VALUE;
@@ -156,11 +208,11 @@ void adc_start (void)
   ADC2->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0
               | ADC_CR1_SCAN);
   ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON;
-  ADC2->SMPR1 = NEUG_ADC_SETTING2_SMPR1;
-  ADC2->SMPR2 = NEUG_ADC_SETTING2_SMPR2;
-  ADC2->SQR1 = ADC_SQR1_NUM_CH(NEUG_ADC_SETTING2_NUM_CHANNELS);
+  ADC2->SMPR1 = config[0];
+  ADC2->SMPR2 = config[1];
+  ADC2->SQR1 = config[2];
   ADC2->SQR2 = 0;
-  ADC2->SQR3 = NEUG_ADC_SETTING2_SQR3;
+  ADC2->SQR3 = config[3];
 
 #ifdef DELIBARATELY_DO_IT_WRONG_START_STOP
   /*
index f0d52fb..c4f1f3f 100755 (executable)
@@ -60,9 +60,9 @@ for option; do
   --vidpid=*)
     vidpid=$optarg ;;
   --enable-sys1-compat)
-    sys1_compat = yes ;;
+    sys1_compat=yes ;;
   --disable-sys1-compat)
-    sys1_compat = no ;;
+    sys1_compat=no ;;
   --with-dfu)
     with_dfu=yes ;;
   --without-dfu)
@@ -256,7 +256,7 @@ then
 fi
 
 if test "$sys1_compat" = "no"; then
-   # Disable when you are sure that it's sys version 2.0.
+   # Disable when you are sure that it's sys version 2.1.
    # Note that Gnuk 1.0 and NeuG (until 0.06) uses sys version 1.0.
    # Disabling the compatibility, executable will be target independent,
    # assuming the clock initialization will be done by SYS (before entry).